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Verilog: add tests for combiations of declarations #362

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merged 1 commit into from
Feb 1, 2024

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@kroening kroening commented Feb 1, 2024

This adds tests for combinations of wire/reg/input/output/inout for the same identifier.

@kroening kroening marked this pull request as ready for review February 1, 2024 19:22
@kroening kroening force-pushed the declaration-tests branch 2 times, most recently from 0554b8c to 6d4d9cc Compare February 1, 2024 19:45
This adds tests for combinations of wire/reg/input/output/inout for the same
identifier.
@tautschnig tautschnig merged commit 4ac2e38 into main Feb 1, 2024
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@tautschnig tautschnig deleted the declaration-tests branch February 1, 2024 20:08
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2 participants